In the semiconductor manufacturing industry, the Moore's Law was always the power that pushed the industry to develop continuously, and Intel made great contributions in that aspect. The development of line width nodes of chips mainly include several stages: 0.18 μm stage—the initial stage of semiconductor process technology, in which MOS tubes became popularized and chips were manufactured in relatively large sizes; 0.13 μm stage—in that stage, people were fairly confident in semiconductor process technology and hoped to reduce chip area and cost by decreasing the feature size; those two stages were usually referred to as micrometer process technology stages. With the developed of nanometer technology, people's vision was no longer limited to micrometer technology but turned to nano-scale semiconductor process technology; 90 nm process technology emerged first; however, as the quantity of tube cores on unit area increased exponentially following the Moore's Law, 65 nm, 45 nm, 32 nm, and current 22 nm process technology emerged successively; the sharp reduction of feature size led to a pursuit for low dielectric loss constant (usually referred to as Low-k) of dielectric materials, for the purpose of reducing parasitic resistance, capacitance, and inductance of circuit structures while ensuring favorable insulating performance of circuits. Porous materials are usually selected for low-k materials; as a result, the materials are relatively brittle and may be fractured under external stress, causing line failures.
Owing to the brittleness of low-k materials, the chip packaging process has to be improved appropriately to adapt to the requirement for product application. Up to now, the packaging of low-k products still employs conventional flip-chip bonding or wire bonding, which results in severe loss of packaging yield. The result of failure analysis indicates that the failure is mainly resulted from fracture of the dielectric layer under bonding electrodes (wire bonding and flip-chip bonding). At present, the solution is to replace wire bonding packaging with flip-chip bonding packaging, and apply non-flow underfill on the substrate before flip-chip bonding. The packaging structure and process are shown in FIG. 1 and FIG. 2. The underfill has features of ordinary underfill and features of reflow flux; therefore, the solder balls and the bonding pad on the substrate can wet each other. A benefit of that method is: injuries to the dielectric layer in the chip under the stress of soldered balls during reflow in the conventional flip-chip packaging process can be alleviated, which is to say, the stress is redistributed via the non-flow underfill, and thereby the dielectric layer in the chip will not be injured owing to stress concentration. However, the biggest disadvantage of that method is that the wetting effect of flux is not enough to ensure every soldered ball can be bonded well to the bonding pad owing to the existence of the underfill; in addition, cavities may occur in the underfill during the curing process owing to the existence of flux and the application of reflow; moreover, the packaging process is complex and requires high cost.
In summary, there are mainly two drawbacks in the low-k chip packaging process at present:    1. With wire bonding and conventional flip-chip technology, stress concentration may occur at the chip electrodes under stress during the technological process, resulting in fracture of the low-k dielectric layer and chip failure;    2. With non-flow backfill in the flip-chip packaging process, poor bonding may exist and cavities may occur in the backfill after curing, causing degraded product reliability.